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FPGA Development Board EP2C8 ALTERA FPGA/NIOS II EP2C8Q208C8 w/ USB Blaster
- FPGA: EP2C8Q208C8
- SDRAM: 64 mbit
- Serial FLASH: 16 mbit (M25P16)
- The parallel FLASH: 16 mbit (2 m * 8 bit)
- 22 * 2 row seat: 2.0 mm
- Number of IO: expand the IO port 93 root (2.54 mm spacing between the extension of the mouth)
- Download: support AS mode and JTAG mode
- Custom indicator light: 4
- Reset button: 1
- Download the light: 1
- Size: 76 * 76 mm
- Package weight:1.2kg
- In order to let the FPGA play its powerful function, black gold development board for its design a resource rich extension board. Here we make a brief introduction of extended board of allocation of resources.
- Network function, configuration ENC28J60 so chips. ENC28J60 is Microchip Technology (Microchip Technology companies in the United States) of 28 pin independent Ethernet controller. On the market at present most of the Ethernet controller of encapsulation were more than 80 pins, and conform to the IEEE 802.3 protocol ENC28J60, only 28 pin can not only provide the corresponding function, and can greatly simplify the related design, reduce the space;
- USB function, configuration CH376 chip. CH376 way support USB devices and USB host, and built the basic firmware of the USB communication protocol, with built-in handle Mass - Storage of Mass Storage device the firmware of special communication protocol, built into the SD card communication interface firmware, built-in FAT16 and FAT32 firmware and FAT12 file system management, support the common USB Storage devices, including USB flash drive/USB hard drive, USB flash drive/USB card reader) and SD card (including standard capacity SD card and high capacity HC - SD card and protocol compatible MMC card and TF card);
- The onboard 128 * 64 dot matrix LCD. ST7565P control chip, the built-in DC/DC circuit, through the software to adjust the contrast. The chip support, parallel and serial port two ways;
- Real time clock (RTC) with DS1302 chip. DS1302 is DALLAS companies in the United States launched a high-performance, low power consumption, real-time clock circuit with the RAM, it can be for the year, month, day, week, timing, minutes and seconds, when have a leap year compensation function, the working voltage of 2.5 V to 5.5 V. Using three line interface with CPU for synchronous communication, and USES the way of breaking a send multiple bytes of the clock signal or RAM data. DS1302 internal have a 31 x 8 RAM registers used for temporary storage of data. DS1302 is DS1202 upgrade products, compatible with DS1202, but increased the main power supply/back power dual power supply pins, at the same time provides the fine trickling water was carried out on the back the power supply current charging ability;
- EEPROM, equipped with 24 lc04 chips. 24 lc04 is 512 * 8 bit block of EEPROM, support IIC interface;
- PS / 2 interface, can realize a PS / 2 keyboard and mouse interface;
- RS232 serial interface, can realize serial data sent and received;
- with digital tube, which can realize the dynamic scanning;
- Five independent key, can cooperate with LCD, construct perfect human-machine interface;
- Color VGA interface, each line has three colors red, respectively, green, and blue. R, G, B signals of different combinations can show eight kinds of color;
- Buzzer, support simple music player;
Point 1: now the sales of the FPGA development board is the latest updated version, on the basis of the original joined a 16 m bit parallel FLASH, the whole system more perfect, can realize dual-core, uclinux higher-end experiment.
Needle point 2: the reserved 34 standard extension interface, by extending the interface, can be extended more functional modules. High speed AD/DA module, for example, 3.2 inch TFT module, etc
Point 3: equipped with a network interface, USB interface, the onboard LCD, and form a complete set of tutorial and the source code.
Point 4: equipped with original NIOS video tutorials, not collected online, is what we entirely original, with the development of sales supporting plate, let you learn more conveniently.