PX Logic 32 32-Channel 1GHz 4G Storage USB3.0 Super High Speed Logic Analyzer with Accessory Kit

PX Logic 32 32-Channel 1GHz 4G Storage USB3.0 Super High Speed Logic Analyzer with Accessory Kit

Project Opensource Address:
- https://github.com/PXLogic/PXView
- If you need to compile a Linux version, please compile it yourself.
- Opensource protocol: GPL V3.

Highlights:
- 4Gbit storage depth
- 1Gsps high sampling rate
- USB3.0 5Gbps
- 200+ decoding protocol
- 0-6V threshold input
- External trigger
- Trigger output
- Multiple hardware filtering
- RLE compress algorithm
- Aluminum alloy shielding shell
- For Win/Mac/Linux

Features and Functions:
- Trigger option: The flat design of the trigger button provides a more comfortable visual effect and allows for more effortless operation. The triggering logic supports nowhere to trigger, rising edge, falling edge, high level, low level, bilateral triggering, supports multiple channel "AND" and "OR", as well as advanced triggering conditions and functions such as protocol triggering.
- Cursor measurement: Mouse following measurement, real-time display of the current signal's pulse width, period, frequency, and duty cycle.
- Label measurement: It can measure any time period and support data parsing and searching between any two labels.

Specification:
- Model: PX Logic 32
- Channel number: 32CH
- USB interface: USB3.0 (Type-C support forward and backward insertion)
- Buffer mode maximum sampling rate: 1GHz/8ch
- Stream mode maximum sampling rate: 1GHz/2ch
- Minimum acquisition pulse width: 2ns
- Maximum hardware storage depth: 4G (bit)
- Data caching mode: Buffer (higher sampling rate)/Stream (longer storage depth)/Roll mode (real-time monitoring)
- Maximum storage depth:
  Buffer Mode: 4G (Bit)
  Stream Mode: depends on computer RAM capacity, up to 1024G (Bit)
- Trigger type:
  Internal trigger: rising edge/high level/falling edge/low level/arbitrary edge
  External trigger: rising edge/high level/falling edge/low level/arbitrary edge
  Trigger output: trigger signal output to IO for external device synchronization
- Protocol support: 200+ protocols (open protocol decoding library, customizable protocols)
- Input withstand voltage: ±40V
- Input impedance: 200K/1pf
- Threshold value: 0 - 6V (0.1V step)
- Waveform output: 1 channel PWM
- Channel interface: 2.54mm DuPont cable interface (50Pin for Nextron, 3U gold-plated JTAG)
- Power supply voltage: 5V/USB power supply
- Power supply current: 300mA (at 5V)
- Power supply power: 1.5W
- Size: 80 x 74 x 13.5mm
- Working temperature: 0 - 85℃ (non-condensing)

Buffer Mode (Max 1Gsps/8ch):
- Buffer Mode (internal hardware cache): Using the internal DRAM of the logic analyzer as the sampling buffer, data is uploaded to the computer after sampling is completed. This mode can provide a higher sampling rate.

Stream Mode (Max 1Gsps/2ch):
- Stream Mode (PC Memory Cache): Using computer memory to store sampling data, which needs to be uploaded to the computer in real time. This mode can provide a larger sampling depth.
- In this mode, it supports up to 128GB (1024Gbit) of memory and theoretically can record data for nearly 17 minutes under a single channel 1Gsps sampling.

Package Included:
- 1 x Logic Analyzer
- 1 x USB 3.2 Data Cable
- 1 x Storage Bag
- 1 x 50Pin 20cm Silicon Cable
- 36 x Logic Probes