DMLogic U2Basic 16CH Logic Analyzer USB 2.0 100MHz Sampling Rate 64Mbits Hardware Memory Debugging

DMLogic U2Basic Technical Parameters:
- USB transfer rate: USB2.0 (480Mbps)
- Supported mode: Buffer (transmission after acquisition, high sampling rate, relatively short acquisition time). Stream (transmit while collecting, the collection time is long, and the sampling rate is relatively low)
- The highest sampling rate (per channel):
  Buffer mode: 100MHz (16 channels)
  Stream mode: 100MHz (3 channels); 50MHz (6 channels); 25MHz (12 channels); 20MHz (16 channels)
- The smallest pulse width that can be collected: 20ns
- The highest signal that can be collected: 25MHz
- Maximum acquisition depth:
  Stream mode: 16G
  Buffer mode: 64Mbits
- The longest acquisition time (stream mode): 160 seconds at 100M sampling rate; 4 hours at 1M sampling rate; 19 days at 10K sampling rate
- Trigger: simple trigger
- Threshold: 0-5V adjustable (0.1V step)
- Withstand voltage range: ±30V
- External interface: for ordinary DuPont line

DMLogic Plus Technical Parameters:
- USB transfer rate: USB2.0 (480Mbps)
- Supported mode: Buffer (transmission after acquisition, high sampling rate, relatively short acquisition time). Stream (transmit while collecting, the collection time is long, and the sampling rate is relatively low)
- The highest sampling rate (per channel):
  Buffer mode: 400MHz (4 channels); 200MHz (8 channels); 100MHz (16 channels)
  Stream mode: 100MHz (3 channels); 50MHz (6 channels); 25MHz (12 channels); 20MHz (16 channels)
- The smallest pulse width that can be collected: 5ns
- The highest signal that can be collected: 100MHz
- Maximum acquisition depth:
  Stream mode: 16G
  Buffer mode: 64Mbits
- The longest acquisition time (stream mode): 160 seconds at 100M sampling rate; 4 hours at 1M sampling rate; 19 days at 10K sampling rate
- Trigger: simple trigger/16-level hardware trigger/protocol trigger
- Threshold: 0-5V adjustable (0.1V step)
- Withstand voltage range: ±30V
- External interface: for ordinary DuPont line

Introduction:
- DMLogic not only supports ordinary protocol parsing, which can directly display the parsed content, but also supports multi-layer protocol stacking, making data display more intuitive and easy to understand, and convenient for debugging.

Supported Basic Protocols:
- For I2C, UART, SPI, CAN, I2S, JTAG, 1-Wire link layer, DMX 512, PWM, Parallel, SWD, USB PD, USB signalling, SWIM, SD card (SD mode), PS/2, MDIO, Stepper motor, Timing, Z80, AC'97, Counter, IR NEC, IR RC-5, AM230x, AUD, AVR PDI, CEC, DALI, DCF77, DSI, EM4100, EM4305, GPIB, Gray code, Guess bitrate, Jitter, LPC, Maple bus, MCS-48, Microwire, Miller, Morse, OOK, Qi, RC encode, RGB LED (WS281x), SDA2506, S/PDIF, ST7735, T55xx, TITLC5620, Wiegand...

Supported High-level Protocols:
- For LIN, 24xx EEPROM, 93xx EEPROM, USB request, USB packet, 1-Wire network layer, AVR ISP, nRF24L01(+), RGB LED(SPI), SD card(SPI mode), SPI flash/EEPROM, Modbus, MIDI, I2C demux, I2C filter, ETMv3, ARM ITM, ARM TPIU, ATSHA204A, DS1307, EDID, LM75, MLX90614, MXC6225XU, Nunchuk, RTC-8564, TITCA6408A, XFP, JTAG/E JTAG, JTAG/STM32, CFP, DS243x, DS28EA00, Oregon, OOK visualisation, ADE77xx, ADF435X, ADNS-5020, MAX7219, MRF24J40, RFM12, SSI32, PAN1321...

Improvements:
- Power chip upgrade: Upgrade from TPS62400DRCR to TLV62569DBVR (2pcs) for TI. Reason: TPS62400DRCR is a dual channel chip with low currents of only 400mA and 600mA. In actual use, it has been found that it is relatively easy to damage. Upgraded to TLV62569DBVR, with a single current of 2A, it was found to be very durable and not easily damaged during testing.
- Upgrade of voltage divider: The old version of the voltage divider is integrated with the test line (visible by cutting open the heat shrink tubing), with a pin spacing of 1.27mm and a voltage divider resistor packaged in 0402 with a resistance value of 100K. The new version of the voltage divider is separated from the test line, with a pin spacing of 2.54mm and a voltage divider resistor packaged in 0603 with a resistance value of 100K. Note: The voltage divider can be omitted for signals below 5V.
- The new version of the voltage divider adapter board's voltage divider resistor packaging has been changed from the old version 0402 to 0603, making it more convenient for users to replace and measure 12V signals. In addition, the new version has transferred the 470R protective resistor from the voltage divider to the interior of the logic analyzer. The advantage of this is that even if you forget to use the voltage divider, it will not burn out the internal protection circuit of the logic analyzer. There is a protective circuit and voltage clamp device inside, and the Iogic0~15 signal will be forcibly clamped to 3.3+0.8V to protect the FPGA port from burning out.

Specification:
- Product size: 16 x 67 x 103mm
- Host net weight: 102g
- Shell material: aluminum alloy

Package Included:
- 1 x Logic Analyzer
- 1 x Testing Clip
- 1 x Voltage Divider Adapter Board
- 1 x USB Type-C Cable