HamGeek SDR-1T8R 70MHz-6GHz SDR Development Board 1TX 8RX 4PCS AD9361 8-Channel Phase Synchronous Reception

Description:
- The SDR-1T8R development board is a highly integrated software defined radio device based on ZYNQ FPGA and 2/4 AD936X RF chips, designed specifically for multi-channel RF signal acquisition, processing, and analysis scenarios. The device implements a multi-channel architecture with 1 transmitter and 4/8 receivers, supporting wideband signal processing from 70MHz to 6GHz. It ensures multi-channel consistency through high-precision phase synchronization technology at the FPGA end and is equipped with ARM bare machine programs and upper computer software to achieve high-speed data transmission, real-time waveform display, flexible trigger control, and other functions.
- This product is suitable for fields such as incoming wave direction detection, signal acquisition, wireless monitoring, radar research and development, communication testing, etc.

Features:
- The firmware implements 8-channel phase synchronization to meet the requirements of phase synchronization for multiple receiving channels in applications.
- Full frequency coverage from 70MHz to 6GHz.
- 0~76dB gain continuously adjustable.
- Default 20M sampling rate, supports customization.
- 1000M Ethernet data transmission.
- Using DDR3 cache and flexible triggering methods, it can continuously collect IQ waveform data up to 16M points.
- Compact size, lightweight design, suitable for size limited scenarios.
- Type-C interface integrates JTAG, PS UART, and power supply functions.

Core Parameters:
- Master chip: XC7Z020-2CLG400I, featuring 85K logic units, 106400 registers, 220 DSP48E1 multipliers, 2.1Mb block RAM, and 4 on-chip PLLs; Integrated ARM Cortex-A9 dual core, with a maximum clock speed of 866MHz, and 32 KB L1 cache and 512 KB L2 cache.
- RF chip: AD9361
- Crystal oscillator: 0.1ppm OCXO
- Triggering source: internal cycle triggering, adjustable cycle, level triggering, external triggering
- Triggering method: single trigger, continuous trigger, delayed trigger, and multiple sampling at equal intervals after triggering
- Trigger storage depth: 16M points
- Storage depth before triggering: 4096 points
- Trigger position: 0 - 4095
- Phase synchronization accuracy: less than 1 degree, supports disabling phase calibration for easy verification of calibration effectiveness
- Extra phase compensation: support additional phase compensation

RF Interface:
- Receiving channel: 8-channel, IPEX interface, 50ohm impedance match
- Transmitting channel: 1-channel, IPEX interface, 50ohm impedance match
- Trigger input: 1-channel, IPEX interface (external trigger signal input)

Power Supply Interface:
- Power supply method: Type-C debugging port power supply; power supply through 2 reserved via holes
- Power supply parameter: 5V DC (±5%), rated current of 2A
- Power consumption specification: typical power consumption about 7W, maximum power consumption ≤10W

Control and Data Interface:
PS Terminal Interface:
- High speed interface: 1-channel Gigabit Ethernet
- 1G bytes 32bit DDR3
- USB-OTG
- SD card slot (support up to 32GB)
- 32M QSPI Flash (used for storing programs and configuration files)

PL Terminal Interface:
- 16-Channel 3.3V GPIO (can be configured as input/output for extended control)

Debugging Interface:
- Integrated into Type-C interface 1 (no additional JTAG interface required, FPGA and ARM joint debugging can be achieved through Type-C cable, while supporting power supply)

Mechanical Dimension and Environment Adaptability:
- Board size: 7 x 8cm
- Net weight: < 100g
- Working temperature: 0℃ to 60℃
- Storage temperature: -40℃ to 85℃
- Relative humidity: 10% to 90% (non-condensing)

RF Function:
- Multi channel synchronization: FPGA side implements multi-channel receiving phase synchronization calibration, supports enabling/disabling phase calibration mode.
- Frequency tuning: Supports continuous tuning across the entire frequency range of 70 MHz to 6 GHz, with a step accuracy of 2Hz.
- Reception gain adjustment: Supports continuous configuration of 0~76dB gain, with a step size of 1dB.
- Self loop testing mode: Supports RF signal self loop testing, facilitating system self checking and debugging.

Signal Processing Function:
- For FPGA side processing: 8-channel synchronous acquisition, phase calibration, data caching, providing high-precision raw IQ data for applications.
- For ARM side processing: Develop bare metal programs based on SDK to achieve data packaging and protocol parsing.
- Data transmission: Multiple reception IQ data are transmitted through UDP protocol, and TCP protocol is used to achieve control command and status interaction.

RF Performance:
- Receiving sensitivity: ≤-95dBm (1GHz, 10MHz bandwidth, SNR=10dB)
- Dynamic range: ≥100dB (SFDR, 1GHz, middle gain)
- Spurious suppression: ≥60dBc (deviation from carrier by more than 1MHz)
- Consistency of 8 receiving channels: phase error ≤1° (full frequency band) 

Package Included:
- 1 x Development Board